SLO-čip
Program
8:30 - 9:00 Registration
 
9:00 – 9:20 Conference Opening
Igor Papič, Minister of Higher Education, Science and Innovation
Polona Köveš, Ministry of Economy, Tourism and Sport
Špela Kern, Ministry of Digital Transformation
Marko Topič, Dean of the Faculty of Electrical Engineering, UL
 
9:20 – 10:30 Global Track
Reseach Activities in Microelectronics (1)
Chair: Janez Krč
9:20 - 9:50 Masoud Agah
Founding and Executive Director, Virginia Alliance for Semiconductor Technology (VAST), USA
VAST Opportunities for Chip Collaboration and Investment in Virginia
9:50 - 10:10 Martin Mischitz
Infineon Technologies Austria AG
Important Project of Common European Interest in Microelectronics and Communication (IPCEI ME/CT)
10:10 - 10:30 Yu-Liang Chung
ITRI, Taiwan
Semiconductor Industry in Taiwan
10:30 - 11:00 Coffee break
 
11:00 – 12:00 Plenary Track
Keynotes
Chair: Andrej Trost
Johannes Sturm
Carinthia University of Applied Sciences, Austria
Integrated Electronic Systems – Status Quo and Future
Clemens Ostermaier
Infineon Technologies Austria AG
GaN power devices: green opportunity and engineering challenge
 
12:00 – 13:00 Competence Centers Track
Reseach Activities in Microelectronics (2) – Competence Centers (CC)
Chair: Andrej Žemva
12:00 - 12:15 Janez Krč
FE UL
Slovenian CC for Chips and Semiconductors
12:15 - 12:30 Tvrtko Mandić
FER UniZg, Croatia
Croatian CC for Chips and Semiconductors
12:30 - 12:45 Robert Gfrerer
Silicon Alps, Austria
Austrian CC for Chips and Semiconductors
12:45 - 13:00 Bruno Paing
CEA-Leti, France
FAMES Pilot Line and the France CC ASTEERICS
 
13:00 - 14:00 Lunch break
 
14:00 – 15:45 Professional Track
Industrial and Academic Research
Chair: Tadej Tuma
14:00 - 14:15 Peter Orel
Stanford University
The VERITAS 2.3 readout ASIC for the ATHENA Wide Field Imager
14:15 - 14:30 Jaka Pribošek
Silicon Austria Labs
Chip-scale optical actuators and sensors
14:30 - 14:45 Gregor Polanšek
Aviat Networks
Chips in the Aviat Networks products
14:45 - 15:00 Adrijan Barić
FER UniZg, Croatia
Influence of Mechanical Stress on Performance of Integrated Circuits – Measurements and Modelling
15:00 - 15:15 Jakup Ratkoceri
University of Twente, The Netherlands
Semiconductor Value Chain and AI enhancement
15:15 - 15:30 Žiga Šmelcer
FE UL
Development of high sensitive THz nanobolometer system
15:30 - 15:45 Miloš Bajič
Instrumentation Technologies
Instrumentation Technologies - Company Introduction
15:45 - 16:15 Coffee break
 
16:15 – 17:45 Masters Competition Track
SLO-Chip Master Contest
Chair: Marko Jankovec
16:15 - 16:30 Andrej Barachini
Renishaw
Voltage doubler design in CMOS technology
16:30 - 16:45 Rok Bunderšek
STMicroelectronics
Losses and efficiency analysis of the RFID system output stage
16:45 - 17:00 Matija Hrušovar
RLS
Development of a dedicated integrated circuit test system
17:00 - 17:15 Matej Kus
ON Semiconductor
Table based register configurator
17:15 - 17:30 Matej Poljanšek
FE UL
Signal processing of microelectromechanical microphones in a programmable circuit
 
17:45 Award Ceremony

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